This invention is in the field of transmitter and receiver circuitry, and is more specifically directed to full duplex transceiver circuitry such as used in modern mobile telephone handsets.
Mobile telephone technology has greatly advanced in recent years, as evident by the higher performance digital mobile telephones now available. To a large extent, these advances stem from the widespread deployment of modern digital wireless modulation technologies such as time division multiple access (TDMA), code division multiple access (CDMA) technologies including conventional CDMA, wideband CDMA (WCDMA), and CDMA2000 standards, and personal communications service (PCS) modulation. The carrier frequencies for these modulated signals ranges from on the order of 800 MHz to as high as 2.0 GHz. These and other digital modulation and communications techniques have greatly improved wireless telephone services, at reduced cost to the consumer.
The circuitry required for carrying out such high-frequency modulation and communication has become increasingly complex. Despite this increasing complexity, there remains significant pressure to further reduce hardware cost. One can reduce cost by reducing the number of integrated circuits and other electronic components used to realize a wireless telephone, as well as by reducing the cost of these integrated circuits by reducing their chip area. However, conventional transceiver circuitry still relies to a large extent on analog circuitry, especially in transmitting and receiving radio frequency (RF) signals. This analog circuitry and passive components such as inductors that are typically required in the analog domain, has limited the extent to which cost reduction and performance improvements, both in operational speed and also reduced power dissipation, can be attained.
FIG. 1 illustrates a conventional architecture for a transmitter in a modern wireless telephone transceiver (transmitter/receiver). As shown in FIG. 1, the digital baseband signal to be transmitted is converted to the analog domain by sigma-delta digital-to-analog converter (DAC) 3. The resulting analog filter is filtered by integrated baseband analog filter 5, and is applied to analog modulator 7. In this conventional architecture, such as is typical for CDMA and WCDMA communications, analog modulator 7 includes first automatic gain control (AGC) function 9, which applies a gain of on the order of 25 to 30 dB prior to analog mixing of the baseband signal with a local oscillator (LO) clock at mixer 11. Typically, mixer 11 is a quadrature mixer, and as such both in-phase (I) and quadrature-phase (Q) components are generated. The LO clock is generated by local oscillator 15, which receives the output of transmit frequency generator function 19. Transmit frequency generator function 19 generates a transmit clock signal based on the output of a voltage-controlled oscillator (VCO) 17 as filtered by loop filter 21. The quadrature output of mixer 11 is applied to second AGC function 13, which applies a 60 dB nominal gain to the signal. Filtering by SAW filter 23 is applied to the output modulated signal, prior to amplification by power amplifier 25.
In this conventional architecture, much of the signal processing is performed in the analog domain. Specifically relative to FIG. 1, the analog domain begins with the output of DAC 3, and continues through analog modulator 7 and power amplifier 25. Because of this large extent of analog processing, the circuitry typically requires several passive components. For the example of the conventional transmitter of FIG. 1, several inductors are necessary, including at the power amplifier stage 25, as well as with analog mixer 11, and also in other circuits within the transmitter. As known in the art, such inductors either must be implemented by external components, or are at best require large chip area if integrated. Other circuits, for example loop filter 21, involve external components (e.g., two resistors and three capacitors).
Analog AGC functions 9 and 13 in this conventional analog transmitter architecture also present issues both in realization and also in operation. As known in the art, the gains applied by AGC functions 9, 13 must be properly calibrated because of their sensitivity to manufacturing process variations and also to operating temperature. This AGC calibration typically involves significant test and characterization time in the manufacturing flow.
As is well known in the art, both the transmitted and received signals occupy the same frequencies in full duplex communications, such as are carried out according to the CDMA and WCDMA standards. Indeed, the largest source of noise in the received signal at a conventional transceiver is typically the leakage from the signals that the transceiver is itself transmitting. However, it has been observed that conventional analog transmitters cannot be constructed to have particularly low receive band noise, particularly if the manufacturing cost is to be kept reasonable (including using reasonable numbers of passive components).
Perhaps most importantly, the analog nature of much of the circuitry of the conventional transmitter of FIG. 1 makes it is difficult to highly integrate this transmitter into a single integrated circuit. Further, as is well known in the art, analog circuitry cannot be readily realized by low-voltage complementary metal-oxide-semiconductor (CMOS) technology. Rather, analog circuitry typically requires bipolar transistors, or at least a combination of bipolar and CMOS devices (e.g., BiCMOS technology), which is expensive from an integrated circuit manufacturing cost standpoint. Bipolar transistors are not as readily scalable as CMOS devices, and as such it is contemplated that the integration efficiency that would be attained by CMOS integrated circuits in the future will not be available to analog circuits utilizing bipolar or BiCMOS technology.